1. Field
This disclosure relates generally to integrated circuits and, more specifically, techniques for checking computer-aided design layers of an integrated circuit device to reduce the occurrence of missing rules in an electronic design automation software deck.
2. Related Art
Designers have employed layout versus schematic (LVS), methodology rule check (MRC), and design rule check (DRC) software (among other electronic design automation (EDA) software) in combination in an attempt to ensure an integrated circuit device (device) layout is correct. In general, MRC has employed a set of rules that attempt to ensure that standard cells are constructed properly. In some cases, MRC may implement rules (that are similar to DRC rules of a DRC deck) that apply to small technology blocks that for various reasons are not included in DRC rules.
Design rules usually include a series of parameters that allow a designer to verify the correctness of a mask set (i.e., a series of electronic data that define geometry for photolithography steps of semiconductor fabrication). In general, design rules are specific to a particular semiconductor manufacturing process. Typically, a design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that devices, when fabricated, function correctly. The most basic design rules are single layer rules, which may include a width rule that specifies a minimum width of any shape in the design and a spacing rule that specifies a minimum distance between two adjacent objects. More complex design rules include multiple layer rules. As another example, a two layer rule may specify a relationship that must exist between two layers. For example, an enclosure rule might specify that an object of one type, such as a contact or via, must be covered with some additional margin by a metal layer. A set of rules for a particular process has typically been referred to as a run-set, a rule deck, or a deck.
In general, a successful DRC ensures that a layout conforms to rules required for faultless fabrication. However, a successful DRC does not guarantee that a layout actually represents a circuit that is supposed to be fabricated. LVS software is usually employed to determine whether a particular integrated circuit layout corresponds to an original schematic or circuit diagram of a design. Early LVS programs operated mainly on the level of graph isomorphism, checking whether a schematic and layout were identical. With the advent of digital logic, isomorphism was too restrictive as the same function could be implemented in many different and non-isomorphic ways. As such, more recent LVS software has been augmented by formal equivalence checking, which checks whether two circuits perform the exact same function without demanding isomorphism. LVS checking software recognizes drawn shapes of a layout that represent electrical components of a circuit, as well as the connections between the electrical components. Connectivity (represented in a netlist) is compared by the LVS software against a schematic or circuit diagram netlist.